Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, 3rd Edition

Once you have written your model, you are not even half done. Developing tests for your designs can take much more time and more code than the original models. Typical designs require three to ten times more effort for creating the tests than for developing the original designs.
You might well ask: "If it takes more time and more code to test a model, why is testing being introduced so late in the book?" The answer is that Verilog makes writing your tests easier by using the same techniques for writing tests as you use to write your models. In this chapter, you will use all the constructs that you have already learned to test models.
While you develop the test suite and behavior model for the alarm model in Chapter 16 or for any other complex system, you will undoubtedly find mismatches between the assumptions of behavior in the model and the assumptions of behavior in the test suite. The differences are resolved by fixing either the model or the test suite, until a single correct set of behaviors is found. The process of enhancing the model and enhancing the test bench can be one of the most time-consuming parts of the design cycle.
Developing a good set of tests can make the difference between a design that behaves properly the first time, and a design that does not perform correctly under some conditions. While you develop your test suites, you can add $monitor,