TABLE OF CONTENTS One of the easiest ways to model designs in Verilog is with structural modeling, which is simply connecting devices. Even complex models can exhibit elements of structural modeling. Whether you are connecting a cache to a processor, or an inverter to an AND gate, you interconnect the models the same way. This chapter shows you how to connect your models. By the end of this chapter, you should be able to model and simulate simple circuits.
Structural modeling is often automated by capturing schematics and writing out netlists. Using structural modeling, you can model many circuits.
Verilog has a set of twenty-six built-in primitives. These primitives represent built-in gates and switches. These built-in primitives are listed in Table 3-1
| Logic Gates | ||
|---|---|---|
| and | or | xor |
| nand | nor | xnor |
| Buffers | ||
| buf | bufif0 | bufif1 |
| not | notif0 | notif1 |
| pulldown | pullup | |
| Transistors | ||
| nmos | pmos | cmos |
| rnmos | rpmos | rcmos |
| tran | tranif0 | tranif1 |
| rtran | rtranif0 | rtranif1 |
The primitives and, nand, or, nor, xor, and xnor represent simple logic functions with one or more inputs and one output. Buffers, inverters, and three-state buffers/inverters are represented by buf, not, bufif1, bufif0, notif1, and notif0. The pullup and pulldown primitives have a single output and no inputs, and are used to pull up or pull down a net. MOS-level unidirectional and bidirectional switches are represented by the remaining primitives.
Appendix A explains each of the primitives in more detail and...
