Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, 3rd Edition

By James M. Lee

Appendix A: Gate-Level Details

OVERVIEW

Chapters 2 and 3 briefly introduced the built-in primitives. This appendix will briefly describe each of the built-in primitives and the options when instantiating them. The delay and strength options for primitive instances will be explained.

PRIMITIVE DESCRIPTIONS

Logic Gates

Figure A-1: AND Gate.

The and primitive can have two or more inputs, and has one output. When all of the inputs are "1" then the output is "1".

Table A-1: Logic Table for *and* Primitive
	0	1	x	z
`0`	`0`	`0`	`0`	`0`
`1`	`0`	`1`	`x`	`x`
`x`	`0`	`x`	`x`	`x`
`z`	`0`	`x`	`x`	`x`

Figure A-2: NAND Gate

The nand primitive can have two or more inputs, and has one output. When all of the inputs are "1" then the output is "0".

Table A-2: Logic Table for *nand* Primitive
	0	1	x	z
`0`	`1`	`1`	`1`	`1`
`1`	`1`	`0`	`x`	`x`
`x`	`1`	`x`	`x`	`x`
`z`	`1`	`x`	`x`	`x`

Figure A-3: OR Gate

The or primitive can have two or more inputs, and has one output. When any of the inputs is "1" then the output is "1".

Table A-3: Logic Table for or Primitive
	0	1	x	z
`0`	`0`	`1`	`x`	`x`
`1`	`1`	`1`	`1`	`1`
`x`	`x`	`1`	`x`	`x`
`z`	`x`	`1`	`x`	`x`

Figure A-4: NOR Gate

The nor primitive can have two or more inputs, and has one output. When any...

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	0	1	x	z
`0`	`0`	`0`	`0`	`0`
`1`	`0`	`1`	`x`	`x`
`x`	`0`	`x`	`x`	`x`
`z`	`0`	`x`	`x`	`x`

	0	1	x	z
`0`	`1`	`1`	`1`	`1`
`1`	`1`	`0`	`x`	`x`
`x`	`1`	`x`	`x`	`x`
`z`	`1`	`x`	`x`	`x`

	0	1	x	z
`0`	`0`	`1`	`x`	`x`
`1`	`1`	`1`	`1`	`1`
`x`	`x`	`1`	`x`	`x`
`z`	`x`	`1`	`x`	`x`

	0	1	x	z
`0`	`0`	`0`	`0`	`0`
`1`	`0`	`1`	`x`	`x`
`x`	`0`	`x`	`x`	`x`
`z`	`0`	`x`	`x`	`x`

	0	1	x	z
`0`	`1`	`1`	`1`	`1`
`1`	`1`	`0`	`x`	`x`
`x`	`1`	`x`	`x`	`x`
`z`	`1`	`x`	`x`	`x`

	0	1	x	z
`0`	`0`	`1`	`x`	`x`
`1`	`1`	`1`	`1`	`1`
`x`	`x`	`1`	`x`	`x`
`z`	`x`	`1`	`x`	`x`

Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, 3rd Edition

TABLE OF CONTENTS

Appendix A: Gate-Level Details

OVERVIEW

PRIMITIVE DESCRIPTIONS

Logic Gates

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	0	1	x	z
`0`	`0`	`0`	`0`	`0`
`1`	`0`	`1`	`x`	`x`
`x`	`0`	`x`	`x`	`x`
`z`	`0`	`x`	`x`	`x`

	0	1	x	z
`0`	`1`	`1`	`1`	`1`
`1`	`1`	`0`	`x`	`x`
`x`	`1`	`x`	`x`	`x`
`z`	`1`	`x`	`x`	`x`

	0	1	x	z
`0`	`0`	`1`	`x`	`x`
`1`	`1`	`1`	`1`	`1`
`x`	`x`	`1`	`x`	`x`
`z`	`x`	`1`	`x`	`x`