Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, 3rd Edition

CATCHING PROBLEMS LATER IN A SIMULATION

Catching an error in simulation can be difficult. If an error occurs early in a simulation, you might catch it with tracing from the start. If an error occurs after a large amount of simulation has occurred, it is often more difficult to find and isolate the problem. Looking through a large amount of trace output to find the problem might take a long time. You could run the simulation without tracing until near the time when you expect the error to occur, and then turn on tracing with $settrace. You can turn off tracing with the $cleartrace command. Tracing always tells you the details of what happened in a simulation.

The traverse-and-observe method is the most common debugging method. However, the trick is to know when to traverse and observe, and to find an easy way to get to the correct simulation time at which to start the traversing and observing.

You have seen how to add a $stop interactively or in your source code to try and stop when you think an error is going to occur. Often you may find that you want to start over again and look at the simulation at an earlier time. The command $reset resets simulation time to 0, so you can start again and set earlier breakpoints or try other techniques.

If you want to have a known point in the simulation to return to and resume simulation from other than...

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