TABLE OF CONTENTS One big advantage of designing with Verilog is the ability to parameterize modules. You can design a generic adder and decide how many bits you need later. You can use the same parameterized adder as a 5-bit adder in one place and as a 64-bit adder elsewhere. Parameters are often used to describe the word size of a module, the number of words in a memory, or even delays. Delays are more commonly set up with a specify block that can be annotated with actual delays from an SDF file.
There are two Verilog keywords associated with parameters: parameter and defparam. When you define a parameterizable module, use the parameter keyword. When you instantiate a parameterized module, you can use the defparam statement to override the default value of parameters in the module.
parameters are used as constants. The only legal way to change the value of a constant is with the defparam statement, parameters and defparam statements are evaluated only during compilation. parameters cannot be changed during simulation time. The values are set at compile time, parameters are by default 32-bit values. It is not common, but the size of a parameter may be changed by specifying a range in the same way wire and register ranges are declared.
Various formats of the parameter statement are shown in Example 14-1.
parameter= ;parameter size = 4;parameter [3:0]...
