TABLE OF CONTENTS Before moving on to Chapter 21, which covers debugging, it may save some time to look at some of the common modeling errors and how to correct them.
One of the first things to double-check in a simulation is the port connections. Mismatched ports are extremely common. They are most common in designs developed by more than one person. Port mismatches are differences between a module's declaration and its connections when instantiated.
There are three types of mismatched port problems:
incorrect number of ports
incorrect size of ports
incorrect order of ports
Verilog warns you if there are too many or too few port connections. Verilog also warns you if the port sizes between the declaration and instantiation are mismatched. There is no single clear warning if the order of ports is mismatched.
Mismatched port order is the most common of the port connection errors. Again, there may be no warning at all if the incorrect hookup results in a legal circuit. Mismatched port order may also result in any number of Verilog error or warning messages. If you switch the order of two signals that are of different sizes, you might get a port size mismatch warning message. If you connect an output port of an instaniated module to a reg in the current module, you may get an error message about an illegal declaration.
The best way to avoid mismatched ports is to adopt some simple rules for port order. For simple modules with one output...
