TABLE OF CONTENTS Chapter 3 discusses structural modeling. Structural modeling is the way to create a hardware hierarchy. Tasks and functions create a software hierarchy similar to subroutines or procedures in a programming language. Tasks and functions may be synthesizable depending on their contents and usage.
In Verilog, you may use a task to encapsulate a behavior. A task is defined in a module and is invoked when its name is called in procedural code. A task has access to all the data objects (nets registers, integers, reals, etc.), so it does not need to have inputs and outputs, though it can have inputs, outputs and inouts. Tasks may take more than zero time to complete; they can have delays, wait statements, and event controls in them. Tasks can be used to apply stimulus, simulate bus cycles, display contents of memories, and many other things. Tasks contain a single statement. If you want a task to have more than a single statement, use a begin-end block or a fork-join block.
Example 11-1 is the hello module modified to use a task.
<a name="436"></a><a name="IDX-126"></a>module hellot;initial begin say_hello; say_hello;endtask say_hello; $display ("Hello Verilog Tasks!");endtaskendmodule The task in Example 11-1, say_hello, is executed when its name ( say_hello) is encountered in the initial block. This task has no inputs or outputs and uses no data. The
