TABLE OF CONTENTS Using the structural modeling technique from Chapter 3, you can model many different types of circuits. One of the reasons that Verilog gained popularity was the ease with which it allowed mixing behavioral modeling techniques with structural modeling. Before Verilog, there were both structural modeling and simulation tools, and there were even behavioral languages and tools, but no one tool combined both behavioral and structural modeling.
Before the creation of Verilog, you needed to know three languages: One for the netlist (as in the structural modeling covered in Chapter 3); one to create the stimulus for your circuit; and one to process the output from the simulation. Using Verilog is more efficient than older simulators: You only need to learn one language. In Verilog, you use the same language for structural modeling, behavioral modeling, creating the stimulus, and analyzing results.
Hopefully you have taken the time to run the simple hierarchical 8-bit adder at the end of Chapter 3. You will note that the results of that simulation give no indication of the inputs and outputs of the circuit, so it is difficult to tell if the circuit really works correctly. Therefore, the first behavioral aspects of the Verilog language we will look at are the parts of the language you use to print results.
Procedural Verilog code is like programming in a computer language with one large exception: Procedural Verilog code adds a concept of time. With a programming language, code...
