TABLE OF CONTENTS It is obviously much easier and less expensive to find and debug an error in your Verilog code than in a completed chip. In Verilog you can watch the exact sequence of events, look at values buried within the circuit, and even see what is driving a multiply driven signal. It takes technique, strategy, and experience to find errors quickly and correct them. This chapter explains a few basic techniques and provides strategies for when to apply those techniques.
During functional debugging, you check the assumptions of behavior in the model against the assumptions of behavior in the test bench, and against the assumptions you make while observing and interpreting results. Debugging can be as simple as manually applying stimulus and looking at the resulting printouts or waveforms. Debugging can get as complicated as trying to determine if an error is in a program running on a simulated computer, in the simulation models, or in the test bench.
One thing to remember about debugging is this: The more information you extract from the simulation, the slower the simulation will go. Printing information to the screen, saving values to a file, or sending signals to a waveform all slow down simulation. If you print out every value in your circuit at every simulation time, the simulator will spend all its time writing out values, and you will spend all your time analyzing them. A more efficient approach is to start out by examining a few critical signals...
