Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, 3rd Edition

Chapter 22: Code Coverage

OVERVIEW

Code coverage is a method by which you measure test benches and models. Code coverage tools can help you answer some difficult questions:

  • Have I created enough test cases?

  • Have I written any code that never gets run?

  • Where are the bottlenecks in my simulation performance?

Code coverage tools answer these questions by monitoring the activity in the simulation and measuring the number of times each statement is executed. Code coverage can be used during the design phase and initial testing phase to find sections or lines of design that are not tested.

Code coverage, sometimes called code profiling, can also be used to increase simulation performance. Simulation performance can be tuned by locating the lines of code the simulator executes most frequently. Once the heavily executed lines have been identified, the designer can look to optimize the heavily executed code.

As designs become more complicated, it is important to measure that every branch of each if and case statement is executed as part of the simulations. If you find statements that are not executed, you need to write more tests that try to exercise the previously non-executed statements. If you cannot write tests that exercise the non-executed parts of your code, you may have cases in which it is not possible to execute those statements. The non-executed statements may require an impossible set of conditions to be executed. In this case the code may be dead code and should be removed. In other cases,...

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