Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, 3rd Edition

In Chapter 1, the phone example used the wait for event (@) operator and the signal event (->) operator. The signal event (->) is an operator that only works with the event data type and the wait for event (@) operator. Events have no value or duration. All they do is indicate something happened. Example 12-1 shows how the signal event operator (->) works.
module show_event;event the_event, something_else;always @ the_event begin $display ("The event happened at time $%0d", $time); -> something_else;end<a name="470"></a><a name="IDX-138"></a>always @ something_else $display ("something else happened");initial begin # 2 -> the_event; # 5 -> something_else; # 1 -> the_event;endendmodule At time 0, both always blocks in Example 12-1 start and wait for their events. At time 2, the initial block signals the_event; the first always block continues, prints its message, and signals the other always block; and the second always block also prints its message. At time 7, the initial statement signals something else and the second block prints its message again. Finally, at time 8, the initial block signals the first always block, which signals the second always block, and both messages print.
The example shown in Example 12-1 has no practical application. What is a good use for the