TABLE OF CONTENTS Verilog has a rich set of procedural statements that can be used for modeling combinatorial logic or sequential logic. This chapter explains the if, case and looping constructs.
A few of the examples from previous chapters have shown the if statement. The if in Verilog has a few quirks. You may have noticed that in Verilog, the if has no corresponding then or endif. Rather, Verilog has an else. The simple form of if is shown in Example 10-1. An if with else is shown in Example 10-2.
if (condition) <i class="emphasis">statement</i>
<a name="390"></a><a name="page110"></a>if <i class="emphasis">(condition) statement</i>else <i class="emphasis">statement</i>
Each branch of an if can only have a single statement. If you need more than one statement, then you need to use a begin-end block or a fork-join block.
The condition can be any expression, or even just a single value. If the condition evaluates to 0 or unknown, then the condition is considered false, and the if clause is not executed. Thus, if the condition evaluates to 1 or more, the if clause is executed, but if it evaluates to 0 or unknown, the else clause executes if it is present.
Because the if has no endif, it is easy to become confused when there are...
