TABLE OF CONTENTS This chapter might be subtitled, Zen and the Art of Verilog Modeling. This chapter marks a departure from the previous chapters (full of syntax and examples) into why you would want to make certain modeling decisions.
Two obvious questions in the construction of a model are, "Will it simulate quickly?" and, "Will it synthesize into what I want to build?" Although simulation performance and synthesis are two considerations for modeling (and the choices you make as you write a model), they are not the only considerations in choosing a modeling style.
So far in this book, the only forces influencing your models have been "write it fast" or "use this new construct." As new constructs were introduced in this book, you were encouraged to use each of them in a model, so the "use this construct" force on modeling style is an artifact of the learning process. The most common force on modeling style is "write it fast." The old adage "haste makes waste" still applies today. A hastily written model may appear to have the correct functionality, but it may be terribly inefficient for simulation, or it may not be synthesizable. As mentioned in Chapter 1, there are three basic reasons for using a hardware description language: Simulation, documentation, and synthesis. Therefore, these three are also forces that act on modeling style.
As shown in Figure 17-1, your modeling style may be affected by different forces. These forces may be pulling your...
