TABLE OF CONTENTS Counters are at the heart of many (or most) sequential systems, so a good understanding of their physical structures is indispensable. To achieve that purpose, an extensive analysis of internal details is presented in this chapter, along with numerous design considerations. The design of counters will be further illustrated in Chapter 15 employing the finite-state-machine concept. Practical designs using VHDL will also be shown in Chapter 22.
Counters can be divided into synchronous and asynchronous. In the former, the clock signal is connected to the clock input of all flip-flops, whereas in the latter the output of one flip-flop serves as clock to the next.
They can also be divided into full-scale and partial-scale counters. The former is modulo-2 N because it has 2 N states (where N is the number of flip-flops, hence the number of bits), thus spanning the complete N-dimensional binary space. The latter is modulo -M, where M < 2 N, thus spanning only part ( M states) of the corresponding binary space. For example, a 4-bit counter counting from 0 to 15 is a full-scale (modulo-16) circuit, while a BCD (binary-coded decimal) counter (4-bits, counting from 0 to 9) is a partial-scale (modulo-10) counter. Synchronous modulo-2 N and modulo -M counters are studied in this section, while their asynchronous counterparts are seen in the next. The following six cases will be described here:
Case 1: TFF-based synchronous modulo-2
