TABLE OF CONTENTS PLL (phase locked loop) circuits are employed for clock multiplication and clock filtration, among other applications. Even though it is not a completely digital circuit, its increasing presence in high-performance digital systems makes its inclusion in digital courses indispensable. For instance, modern FPGAs (Section 18.4) are fabricated with several PLLs.
A basic PLL is depicted in Figure 14.25, which generates a clock whose frequency ( f out) is higher than that of the input (reference) clock ( f in). The circuit operates as follows. The VCO (voltage-controlled oscillator) is an oscillator whose frequency is controlled by an external DC voltage. When operating alone, it generates a clock whose frequency is near the desired value, f out. This frequency is divided by M in the prescaler, resulting f loop= f out/ M, which might be near f in, but is neither precise nor stable. These two signals ( f loop and f in) are compared by the PFD (phase-frequency detector). If f loop < f in, then the PFD commands the charge pump to increase the voltage applied to the VCO (this voltage is first filtered by a low-pass loop filter to attain a stable operation), thus causing f out to increase and, consequently, increasing f loop as well. On the other hand, if f loop > f in, then the opposite happens, that is, the PFD commands...
