TABLE OF CONTENTS This section describes the generation of irregular square waves, which constitutes a typical application for counters. By definition, a signal generator is a circuit that takes the clock as its main input and from it produces a predefined glitch-free signalat the output.
The design technique described here is a simplified procedure. In Chapter 15, a formal design technique, based on finite state machines, will be studied, and in Chapter 23 such a technique will be combined with VHDL to allow the construction of more complex signals. As will be shown, the main drawback of a simplified procedure is that it is more difficult to minimize the number of flip-flops. The overhead in this design, however, is just one flip-flop, and the counter employed in the implementation is a regular binary counter (Sections 14.2 and 14.3).
An example of a signal generator is depicted in Figure 14.18. The only input is clk, from which the signal called q must be derived. Because q must stay low during three clock periods and high during five periods (so T = 8 T 0), an eight-state counter is needed. This means that there exists a circuit, which employs only three flip-flops (because 2 3 = 8), whose MSB corresponds to the desired waveform. The problem is that such a counter is not a regular (sequential) binary counter because then the outputs would look like those in Figure 14.3(c), where q 2 is not equal...
