14.9 Exercises

1. Circular shift register

   Draw a diagram for a circular SR whose rotating sequence is "00110" (see Figure 14.2(c)).

2. SR timing analysis

   Suppose that the propagation delay from clk to q in the DFFs employed to construct the SR of Figure 14.2(a) is t _pCQ = 5 ns. Assuming that the circuit is submitted to the signals depicted in Figure E14.2, where the clock period is 30 ns, draw the resulting output waveforms (adopt the simplified timing diagram style of Figure 4.8(b)).

   
   Figure E14.2

3. Event counter

   Consider the waveform x depicted in Figure E14.3. How can we design a circuit that counts all events that occur on x (that is, rising plus falling edges)? (Hint: Think about who could be the LSB).

   
   Figure E14.3

4. Synchronous 0-to-31 counter with TFFs

   1. Draw a circuit for a synchronous 0-to-31 counter with parallel enable using regular TFFs.

   2. Repeat the design above, this time with serial enable.

5. Synchronous 0-to-31 counter with DFFs

   1. Draw a circuit for a synchronous 0-to-31 counter with parallel enable using regular DFFs.

   2. Repeat the design above, this time with serial enable.

6. Synchronous 0-to-255 counter with TFFs

   Draw a circuit for a synchronous 0-to-255 counter with serial enable using regular TFFs.

7. Synchronous 0-to-255 counter with DFFs

   Draw a circuit for a synchronous 0-to-255 counter with serial enable using regular DFFs.

8. Synchronous 0-to-4 counter with TFFs

   1. Design a synchronous 0-to-4 binary counter using regular TFFs (see Example 14.1).

   2. Draw a timing diagram for your circuit (consider...