TABLE OF CONTENTS Objective: This chapter concludes the study of sequential circuits (initiated in Chapter 13). A formal design procedure, called finite state machine (FSM), is here introduced and extensively used. The FSM approach is very helpful in the design of sequential systems whose operation can be described by means of a well-defined (and preferably not too long) list containing all possible system states, along with the necessary conditions for the system to progress from one state to another, and also the output values that the system must produce in each state. This type of design will be further illustrated using VHDL in Chapter 23.
Chapter Contents
| 15.1 | Finite State Machine Model |
| 15.2 | Design of Finite State Machines |
| 15.3 | System Resolution and Glitches |
| 15.4 | Design of Large Finite State Machines |
| 15.5 | Design of Finite State Machines with Complex Combinational Logic |
| 15.6 | Multi-Machine Designs |
| 15.7 | Generic Signal Generator Design Technique |
| 15.8 | Design of Symmetric-Phase Frequency Dividers |
| 15.9 | Finite State Machine Encoding Styles |
| 15.10 | Exercises |
| 15.11 | Exercises with VHDL |
The specifications of a sequential system can be summarized by means of a state transition diagram, like that depicted in Figure 15.1. What it says is that the machine has four states, called stateA, stateB, stateC, and stateD; it has one output, called y, that must be 0 when in stateA, stateB, or stateC, or 1 when in stateD; and it has one input (besides clock, of...
