TABLE OF CONTENTS A clock (or frequency) divider is a particular type of two-window signal generator, which takes the clock as input and produces at the output a signal whose period ( T) is a multiple of the clock period ( T 0). Depending on the application, the phase of the output signal might be required to be symmetric (duty cycle = 50%). The design procedure described here is again a simplified procedure, so the same observations made in the previous section are valid here (like the need for an extra flip-flop and the use of finite state machines to minimize their number). However, contrary to Section 14.4, dual-edge generators will be included in this section, where the following five cases are described:
Case 1: Divide-by-2N
Case 2: Divide-by-M with asymmetric phase
Case 3: Divide-by-M with symmetric phase
Case 4: Circuits with multiple dividers
Case 5: High-speed frequency dividers (prescalers)
To divide the clock frequency by 2 N (where N is a positive integer), the simplest solution is to use a regular (sequential) modulo-2 N binary counter (Sections 14.2 and 14.3), whose MSB will automatically resemble the desired waveform. In this case, the number of flip-flops will be minimal, and the output signal will exhibit symmetric phase (duty cycle = 50%) automatically (see Figures 14.3(c) and 14.15(d)).
To divide the clock by M (where M is a nonpower-of-2 integer), any modulo-
