Digital Electronics and Design with VHDL

14.8: Scramblers and Descramblers

14.8 Scramblers and Descramblers

As mentioned in Sections 6.1 and 6.9, scramblers are circuits that pseudo-randomly change the values of some bits in a data block or stream with the purpose of "whitening" its spectrum (that is, spread it so that no strong spectral component will exist, thus reducing electromagnetic interference) or to introduce security (as part of an encryption procedure). The pseudo-randomness is normally accomplished using an LFSR circuit (described in the previous section). In this case, a scrambler is just an LFSR plus an additional modulo-2 adder (XOR gate), and it is specified using the LFSR's characteristic polynomial.

There are two types of LFSR-based scramblers, called additive and multiplicative (recursive) scramblers. Both are described below, along with their corresponding descramblers.

14.8.1 Additive Scrambler-Descrambler

Additive scramblers are also called synchronous (because they require the initial state of the scrambler and descrambler to be the same) or nonrecursive (because they do not have feedback loops). A circuit of this type is shown in Figure 14.32(a), where a simplified representation similar to that in Figure 14.30(c) was employed. Its characteristic polynomial (which is the LFSR's polynomial) is 1+ x 9+ x 11 because the taps are connected at the output of registers 9 and 11. This is the scrambler used in the 100Base-TX interface described in Section 6.1, which repeats its sequence after 2 N ?1 = 2047 bits.


Figure 14.32: (a) Additive scrambler with polynomial 1 + x 9 + x 11

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