TABLE OF CONTENTS Objective: As mentioned earlier, VHDL allows circuit synthesis as well as circuit simulation. In the preceding chapters we concentrated on the former, so all VHDL statements and constructs employed there are synthesizable. We turn now to circuit simulation, where fundamental simulation procedures are introduced and then illustrated by means of complete examples. A brief tutorial on ModelSim, a popular simulator for VHDL-based designs, which was employed to simulate all examples shown in this chapter, is included in Appendix A.
Chapter Contents
| 24.1 | Synthesis versus Simulation |
| 24.2 | Testbench Types |
| 24.3 | Stimulus Generation |
| 24.4 | Testing the Stimuli |
| 24.5 | Testbench Template |
| 24.6 | Writing Type I Testbenches |
| 24.7 | Writing Type II Testbenches |
| 24.8 | Writing Type III Testbenches |
| 24.9 | Writing Type IV Testbenches |
| 24.10 | Exercises |
VHDL is intended for circuit synthesis as well as circuit simulation. Synthesis is the process of translating a source code into a set of hardware structures that implement the functionalities described in the code. Circuit simulation, on the other hand, is a testing procedure used to ensure that the synthesized circuit does implement the intended behavior (normally performed before any physical implementation actually takes place).
The general simulation procedure is illustrated in Figure 24.1, which shows the design under test (DUT) in the center, the stimuli applied to the DUT on the left, and the corresponding DUT's response on the right. Two VHDL files are mentioned, referred to as design file and test file. The former...
