TABLE OF CONTENTS Objective: This chapter describes CPLD and FPGA devices. Owing to their high gate/flip-flop density, wide range of I/O standards, large number of I/O pins, easy ISP (in-system programming), high speed, and decreasing cost, their presence in modern digital systems has grown substantially. Additionally, the ample diffusion of VHDLand Verilog, plus the high quality of current synthesis and simulation tools, also contributed to the wide adoption of such technology. CPLD/FPGA devices allow the development of new products with a very short time to market, as well as easy update or modification of existing circuits.
Chapter Contents
| 18.1 | The Concept of Programmable Logic Devices |
| 18.2 | SPLDs |
| 18.3 | CPLDs |
| 18.4 | FPGAs |
| 18.5 | Exercises |
Programmable logic devices (PLDs) were introduced in the mid 1970s. The idea was to construct combinational logic circuits that were programmable. However, contrary to microprocessors, which can run a program but possess a fixed hardware, the programmability of PLDs was intended at the hardware level. In other words, a PLD is a general purpose chip whose hardware can be configured to meet particular specifications.
The first PLDs were called PAL (programmable array logic) or PLA (programmable logic array), depending on the programming scheme (described later). They employed only conventional logic gates (no flip-flops), therefore targeting only the implementation of combinational circuits. To extend their coverage, registered PLDs were launched soon after, which included one flip-flop at each circuit output. With them, simple sequential
