TABLE OF CONTENTS Objective: This tutorial, which is a complement to Chapter 24, briefly describes ModelSim, from Mentor Graphics, a popular simulator for VHDL- and Verilog-based designs. The tutorial is based on ModelSim-Altera Web Edition 6.1g, available free of charge from www.altera.com.
The presentation is divided into two parts, as follows:
Part I: Simulation Procedure
In this part of the tutorial the simulation files are entered directly into the simulation environment, and the steps needed to process them are described.
Part II: Creating a New Project
In this case a project is created before entering the simulation files, which improves code organization and reusability. The subsequent simulation procedure is exactly the same as that in Part I.
A simplified view of ModelSim's components and respective design flow is presented in Figure A.1. The diagram shows the VHDL (or Verilog) files at the top, which are combined with the VHDL (or Verilog) libraries by the first two components, vlib and vmap. Next appears the compiler ( vcom for VHDL, vlog for Verilog), and finally the simulator ( vsim).
As seen in Chapter 24, at least two files are needed to simulate a circuit. One is referred to as the design file because it must contain the code from which the DUT is inferred. The other is referred to as the test file because it contains the testbench (input stimuli plus, optionally, output...
