TABLE OF CONTENTS Asynchronous counters require less hardware space (and generally also less power) than their synchronous counterparts. However, due to their serial clock structure, they are also slower. The following cases will be described:
Case 1: Asynchronous modulo-2N counters
Case 2: Asynchronous modulo-M counters
Figure 14.15 shows classical asynchronous full-scale counter implementations. In Figure 14.15(a), all flip-flops are TFFs, with no toggle-enable input ( t). The actual clock signal is applied only to the first flip-flop and the output of each stage serves as input (clock) to the next stage. This circuit (as well as all the others in Figure 14.15) is a downward counter because it produces q 3 q 2 q 1 q 0= {"1111" ?"1110" ?"1101" ? ?"0000" ?"1111" ? }, where q 0 is again the LSB. This sequence can be observed in the partial timing diagram shown in Figure 14.15(d). Notice that q 0 is one TFF-delay behind clk, q 1 is two TFF-delays behind clk, and so on. In Figure 14.15(b), the most common choice for the TFF's internal structure is depicted (DFF-based), which corresponds to that seen in Figure 13.24(a). Finally, in Figure 14.15(c), the same type of counter is shown but now with a counter-enable input ( ena), which is connected to the t (toggle-enable) input of each TFF. When ena = 1 , the counter operates as usual, but...
