TABLE OF CONTENTS Objective: This chapter concisely describes the VHDL language and presents some introductory circuit synthesis examples. Its purpose is to lay the fundamentals for the many designs that follow in Chapters 20 and 21, for combinational circuits, and in Chapters 22 and 23, for sequential circuits. The use of VHDL is concluded in Chapter 24, which introduces simulation techniques with VHDL testbenches. The descriptions below are very brief; for additional details, books written specifically for VHDL ([Pedroni04a] and [Ashenden02], for example) should be consulted.
Chapter Contents
| 19.1 | About VHDL |
| 19.2 | Code Structure |
| 19.3 | Fundamental VHDL Packages |
| 19.4 | Predefined Data Types |
| 19.5 | User Defined Data Types |
| 19.6 | Operators |
| 19.7 | Attributes |
| 19.8 | Concurrent versus Sequential Code |
| 19.9 | Concurrent Code ( WHEN, GENERATE) |
| 19.10 | Sequential Code ( IF, CASE, LOOP, WAIT) |
| 19.11 | Objects ( CONSTANT, SIGNAL, VARIABLE) |
| 19.12 | Packages |
| 19.13 | Components |
| 19.14 | Functions |
| 19.15 | Procedures |
| 19.16 | VHDL Template for FSMs |
| 19.17 | Exercises |
The summary presented in this chapter can be divided into two parts [Pedroni04a]. The first part, which encompasses Sections 19.1 to 19.11, plus Section 19.16, describes the VHDL statements and constructs that are intended for the main code, hence referred to as circuit-level design. The second part, covered by Sections 19.12 to 19.15, presents the VHDL units that are intended mainly for libraries and code partitioning, so it is referred to as system-level design.
VHDL is a technology and vendor independent hardware description language. The code describes the...
