TABLE OF CONTENTS Objective: Sequential circuits were studied in Chapters 13 to 15, with regular circuits in Chapters 13 and 14 and finite state machine (FSM)-based circuits in Chapter 15. The same division is made in the VHDL examples, with regular sequential designs presented in this chapter and FSM-based designs shown in the next. This chapter closes with a larger example in which the design of neural networks is illustrated.
Chapter Contents
| 22.1 | Shift Register with Load |
| 22.2 | Switch Debouncer |
| 22.3 | Timer |
| 22.4 | Fibonacci Series Generator |
| 22.5 | Frequency Meters |
| 22.6 | Neural Networks |
| 22.7 | Exercises |
Figure 22.1 shows an M-stage N-bit shift register (SR) with load capability (this circuit was studied in Section 14.1). When load = 1 , vector x must be loaded into the SR at the next rising clock edge, while for load = 0 the circuit must operate as a regular SR. We illustrate in this section the design of such SR under the following two premises: (i) M and N generic and (ii) employing a structural design approach (with COMPONENT used to instantiate the multiplexers and flip-flop banks).
A VHDL code for this circuit is shown below. Because M and N must be arbitrary values, a user-defined data type is needed for x because none of the predefined types (Figure 19.4) satisfy the present need. Because such a type...
