Last revised: October 23, 2024
Reviewed by: Scott Orlosky, consulting engineer

Analog-to-digital converter chips (ADCs) transform information from analog to digital form. ADCs receive analog input, perform calculations on the analog signal, and then digitally encode the output in a format that computerized systems can process. Analog-to-digital converter chips are used in a variety of applications, including data-acquisition, communications, instrumentation, and signal processing. To cover a broad range of performance needs, ADCs are available in different resolutions, bandwidths, accuracies, packaging, power requirements, and temperature ranges.

Successive-approximations register (SAR) and flash are two common architectures for analog-to-digital converter chips. SAR architecture uses a single comparator and multiple conversion cycles. Flash, or parallel, architecture uses multiple comparators and a single conversion cycle. With flash, ADCs use a set of 2ⁿ-1 comparators to measure an analog signal to a resolution of n bits. Consequently, flash ADCs are faster than SAR ADCs, but require a greater number of comparators.

Pipeline architecture overcomes some of the limitations of flash architecture by dividing the conversion task into several consecutive stages. Each stage consists of a sample and hold circuit, an m-bit ADC (e.g., a flash converter), and an m-bit digital-to-analog converter (DAC). In this way, pipelined converters achieve higher resolutions than flash converters containing a similar number of comparators. However, pipeline analog-to-digital converter chips increase the total conversion time from one cycle to p cycles.

Another approach, subranging, combines flash, SAR, and pipeline architectures and breaks n-bit conversions into m-bit sub-conversions. Like pipeline architecture, subranging consists of several cascading stages, each of which uses a low-resolution analog-to-converter chip to estimate the input and an accurate DAC to convert the output. Subranging also calculates the residue, the difference between the estimated input and the actual output. A gain block is used to amplify and restore the residue to an appropriate level for further estimation by the next stage.

Sigma-delta architecture takes a fundamentally different approach than other ADC architectures. Sigma-delta converters consist of an integrator, a comparator, and a single-bit DAC. The DAC output is subtracted from the input signal, the resulting signal is integrated, and the comparator converts the integrator output voltage to a single-bit digital output (1 or 0). The resulting bit becomes the DAC’s input, and the DAC’s output is subtracted from the ADC’s input signal. With sigma-delta architecture, the digital data from the ADC is a stream of ones and zeros, and the value of the signal is proportional to the density of digital ones from the comparator. This bit stream data is then digitally filtered and decimated to result in a binary-format output.

Analog-to-Digital Converter (ADC) Chips FAQs

How do different ADC architectures impact performance characteristics like speed and resolution?

Different ADC architectures impact performance characteristics such as speed and resolution in various ways.

Successive Approximation Register (SAR) ADCs

Speed: SAR ADCs are relatively slow because they perform serial comparisons and must pause at each step to set the DAC and wait for its output to settle. However, they can achieve conversion rates over 1 MHz.

Resolution: Typically, SAR ADCs offer resolutions of 8 to 16 bits. They are widely used due to their balance of speed, accuracy, and cost-effectiveness.

Sigma-Delta ADCs

Speed: Sigma-Delta ADCs tend to be slower because they use a decimation filter, which reduces the sample rate.

Resolution: They can achieve high resolutions, typically ranging from 16 to 24 bits. However, the effective accuracy might be lower due to noise, which can be mitigated using digital filter algorithms.

Folding ADCs

Speed: Folding ADCs can operate at very high speeds, making them suitable for applications requiring fast data conversion. Each Folding Amplifier (FA) in a folding ADC provides a non-linear response that folds the input signal around half of its input range.

Flash and Pipelined (Subranging) ADCs

Speed: These architectures are widely used where high sampling rates are required.

Resolution: They are generally used in applications where speed is prioritized over resolution.

Voltage-to-Frequency and Integrating ADCs

Speed and Resolution: These types of ADCs offer a range of resolutions and speeds, with integrating ADCs providing higher resolutions but at lower speeds.

What are the trade-offs between speed and resolution in ADCs?

The trade-offs between speed and resolution in ADCs are a fundamental consideration in selecting the appropriate ADC architecture for a given application.

Speed: Refers to how quickly an ADC can convert an analog signal to a digital one. It is often measured in samples per second (sps) or conversions per second.

Resolution: Indicates the number of bits used to represent the analog input in digital form. Higher resolution means more precise representation of the input signal.

Higher Speed, Lower Resolution: ADCs designed for high-speed applications, such as flash and pipelined ADCs, often sacrifice resolution to achieve faster conversion rates. These are suitable for applications like video processing where speed is critical, but extremely high precision is not as necessary.

Higher Resolution, Lower Speed: Sigma-Delta ADCs, for example, offer high resolution (16 to 24 bits) but are generally slower due to the use of decimation filters. These are ideal for applications requiring precise measurements, such as audio processing or instrumentation.

Balanced Approach: Successive Approximation Register (SAR) ADCs provide a balance between speed and resolution, typically offering resolutions of 8 to 16 bits with conversion rates over 1 MHz. They are widely used in applications where a moderate level of both speed and resolution is required.

The choice of ADC architecture should be based on the specific requirements of the application, considering factors such as power consumption, cost, and the nature of the signal being converted.

For instance, in battery-powered devices, power efficiency might be prioritized over speed or resolution.

What is the impact of ADC architecture on power consumption?

The impact of ADC architecture on power consumption is influenced by several factors, including the type of architecture, supply voltage, resolution, and speed. Here's a detailed explanation.

Successive Approximation Register (SAR) ADCs: These are known for their speed and robustness, which might come at the cost of higher power consumption due to a larger die area. SAR ADCs offer a good combination of speed, accuracy, and noise immunity, but this can lead to increased power usage.

Sigma-Delta ADCs: These typically require less die area and are relatively easy to implement, which can make them more power-efficient compared to SAR ADCs. However, they tend to be slower due to the use of decimation filters.

Modern ADCs operate at lower supply voltages, such as 3V or 5V, compared to older models that used 15V supplies. Lower supply voltages can reduce power consumption but also introduce challenges like increased susceptibility to noise.

Higher resolution and faster conversion rates generally require more power. Therefore, there is often a trade-off between achieving high performance and maintaining low power consumption.

The specific requirements of the application, such as whether it is battery-powered or requires high precision, will influence the choice of ADC. For instance, in battery-powered devices, power efficiency might be prioritized over speed or resolution.

Proper design and layout techniques, such as grounding and decoupling, are crucial to minimize power consumption and noise susceptibility in ADCs operating at lower supply voltages.

What are some techniques to reduce power consumption in ADCs?

To reduce power consumption in ADCs, several techniques can be employed, focusing on architecture choice, supply voltage, and design considerations.

Sigma-Delta ADCs: These are typically more power-efficient compared to SAR ADCs because they require less die area and are easier to implement. Choosing an architecture that inherently consumes less power can be beneficial.

Operating ADCs at lower supply voltages, such as 3V or 5V, can significantly reduce power consumption compared to older models that used 15V supplies. However, this also requires careful design to manage increased noise susceptibility.

Reducing the resolution or conversion speed can lower power consumption. Higher resolution and faster conversion rates generally require more power, so balancing these parameters according to application needs can help manage power usage.

Proper grounding, decoupling, and layout techniques are crucial to minimize power consumption and noise susceptibility, especially in ADCs operating at lower supply voltages.

Tailoring the ADC choice to the specific needs of the application, such as prioritizing power efficiency in battery-powered devices, can lead to significant power savings.

These techniques can help in optimizing the power consumption of ADCs while maintaining the necessary performance characteristics for specific applications.

The differences in power consumption between Successive Approximation Register (SAR) ADCs and Sigma-Delta ADCs can be attributed to their architectural characteristics and operational requirements.

SAR ADCs: These ADCs are known for their speed and robustness, which might come at the cost of higher power consumption due to a larger die area. They offer high-speed voltage conversion and excellent noise immunity, but this can lead to increased power usage.

Sigma-Delta ADCs: These ADCs typically require less die area and are relatively easy to implement, which can make them more power-efficient compared to SAR ADCs. However, they tend to be slower because they use a decimation filter.

Both types of ADCs can operate at lower supply voltages, such as 3V or 5V, which can help reduce power consumption compared to older models that used higher supply voltages. However, lower supply voltages also introduce challenges like increased susceptibility to noise.

Higher resolution and faster conversion rates generally require more power. SAR ADCs, which are designed for speed, might consume more power to achieve high conversion rates. In contrast, Sigma-Delta ADCs, which focus on high resolution, might be more power-efficient due to their slower operation and smaller die area.

Analog-to-Digital Converter (ADC) Chips Media Gallery

References

GlobalSpec—Digital Techniques for Wideband Receivers, Second Edition

GlobalSpec—Sensor Technology Handbook

Image credit:

Intersil Corporation